1. Field of the Invention
This invention relates to a substrate bias generator enclosed in a semiconductor integrated circuit device, such as a memory.
2. Description of the Prior Art
In a semiconductor integrated circuit device, such as a memory, a substrate voltage V.sub.BB in the order of -2 to -3.5 V is supplied to a semiconductor substrate for effectively retaining data stored in memory cells. This substrate voltage V.sub.BB is set so as to be at a value lower than the ground voltage (0 V) and is supplied to the substrate by a pumping operation by capacitors, as disclosed for example in Japanese Patent KOKAI (Laid-Open) Publication No. 1-154395(1989).
FIG. 1 shows an example of the conventional substrate bias generator. An oscillator, not shown, supplies anti-phase clock pulses by means of inverters 7 and 8 to a pair of capacitors 1 and 2, each formed by a pMOS transistor, so that these capacitors 1 and 2 will perform alternate charge-pumping operations. Rectifying pMOS transistors 3 and 4 are connected to a terminal P.sub.0 of the capacitor 1 and a terminal Q.sub.0 of the capacitor 2, respectively, while being connected in common to a mode 9 from which the substrate voltage V.sub.BB is outputted. A pair of pMOS transistors 5 and 6 for discharging to a grounding line, which is at 0 V or at the GND level, are connected to the terminal P.sub.0 and Q.sub.0, respectively.
The operation of the above described circuit is hereinafter explained briefly. It is first assumed that, with the level of the terminal R.sub.0 of the capacitor 1 at the "H" level, or at 5 V, and with the terminal P.sub.0 of the capacitor 1 at the GND level due to discharging by means of the pMOS transistor 5, the voltage level at the terminal R.sub.0 has been shifted by the inverter 7 from the "H" level to the "L" level or to 0 V. The voltage level at the terminal P.sub.0 of the capacitor 1 is lowered at this time from approximately 0 V to close to -5 V. However, when the voltage level exceeds the threshold voltage Vth of the pMOS transistor 3, the pMOS transistor 3 is turned on. Simultaneously, the gate voltage of the pMOS transistor 5 is at the voltage level at the terminal Q.sub.0, so that the transistor 4 is turned off. Thus the voltage level at the terminal P.sub.0 is raised by the current from the node 9 to a value in the vicinity of the substrate voltage V.sub.BB plus threshold voltage (V.sub.BB +Vth). When the voltage at the terminal R.sub.0 shifts to the "H" level, the voltage level at the terminal P.sub.0 is also raised so as to follow the voltage shift at the terminal R.sub.0. Thus the pMOS transistor 3 is turned off, while the pMOS transistor 5 is turned on, as a result of which the voltage at the terminal P.sub.0 is again reset to close to the ground level. Such charge pumping operation occurs simultaneously with the capacitor 2 and the pMOS transistors 5 and 6, so that substrate charges are drained alternately from the node 9 by means of pMOS transistors 5 and 6 to maintain a predetermined value of the substrate voltage V.sub.BB.
However, the conventional circuit shown in FIG. 1 is inconvenient in that its pumping efficiency can not be raised sufficiently.
That is, while the pMOS transistor 3 is formed in an n-well on the p-type semiconductor substrate, the n-well is connected to the terminal R.sub.0, as shown in FIG. 1, and is alternately supplied with the source voltage Vcc and the ground voltage GND. However, if our attention is directed to the pMOS transistor 3, the voltage level at the node 9 is approximately -2 to -3 V almost steadfastly, so that, during the turn-on period of the transistor 3, the n-well voltage becomes higher about 2 to 3 V than the source voltage. As a result, the threshold voltage Vth of the pMOS transistor 3 is raised. Referring to FIG. 2, which is a waveform diagram of the circuit shown in FIG. 1, while the voltage at the terminal P.sub.0 becomes fixed at a level lower than the substrate voltage V.sub.BB by the threshold voltage Vth.sub.0 for the low voltage level at the terminal R.sub.0, the larger the threshold voltage Vth.sub.0, the higher becomes the rate of decrease of the amount of charges passing through the pMOS transistor 3, so that the charge draining efficiency at the mode 9 is correspondingly lowered. The same also applies to the pMOS transistor 4.